1. Field of the Invention
The present invention relates to a low power semiconductor memory device having a normal mode and a partial array self refresh mode and, more particularly, to a semiconductor memory device capable of remarkably reducing power consumption on stand-by by optimizing a refresh period in a partial array self refresh mode, by using a point that each bank has different refresh properties.
2. Description of the Related Art
Recently, there is a great demand for mobile systems such as cellular phones and personal digital assistants (PDA""s). Therefore, it is required to develop a current-saving DRAM for these systems. A partial array self refresh mode has been proposed in order to meet these needs. The partial array self refresh mode is a method whereby when the amount of memory used is small and therefore, it is unnecessary to access all banks, only a predetermined bank is accessed in a system, thereby remarkably reducing the power consumption of chip. Here, the refresh is also performed only in the predetermined bank.
However, in a conventional system, a predetermined bank is generated in the partial array self refresh mode and provided to a bank unit. Therefore, the bank accessed in the partial array self refresh mode is identical in all memories having the same structures. However, although the structures are identical, bank refresh properties may be changed due to various reasons. Therefore, there are cases in which the bank, selected as default by the memory control unit, is not one having optimized refresh properties and it is impossible to employ the refresh properties of another bank. As a result, the conventional system has a disadvantage in that, when the predetermined bank has poor refresh properties, power consumption is increased due to short refresh period, thereby generating serious problems in the mobile system, using battery power and lowering stability of data maintenance.
Therefore, the present invention has been made to solve the above problems and an object of the present invention is to provide a semiconductor memory device capable of lowering power consumption in a partial array self refresh mode.
Another object of the present invention is to provide a semiconductor memory device capable of improving stability of data maintenance in a partial array self refresh mode.
In order to accomplish these objects, the bank selection signal generating unit of the present invention receives a pre-bank selection signal of a memory control unit to generate a bank selection signal for practically selecting a bank by using the pre-bank selection signal in a normal mode and to generate a bank selection signal for selecting a bank having optimized refresh properties in a partial array self refresh mode, without using the pre-bank selection signal.
The bank selection signal generating unit comprises a bank selection fuse circuit for outputting a signal indicating a bank to be selected in a partial array self refresh mode, and a bank selection circuit for passing the pre-bank selection signal to generate a bank selection signal in a normal mode and for inverting the pre-bank selection signal according to the output signal of the fuse circuit to generate a bank selection signal in a partial array self refresh mode.
The present invention further comprises a self refresh period signal generating unit for providing a self refresh period signal to a plurality of banks. The self refresh period signal generating unit provides a self refresh period signal, having a period most suitable for refresh properties of the bank selected by the bank selection signal in a partial array self refresh mode, to a predetermined bank selected in the partial array self refresh mode. The refresh period signal generating unit comprises a period signal generating circuit for generating a plurality of period signals having different periods; a period selection fuse circuit for outputting a signal indicating the self refresh period of a bank selected by the bank selection signal in the partial array self refresh mode; and a period signal selection circuit for selecting and outputting one period signal of a plurality of period signals in the period signal generating circuit by using the output signal of the period selection fuse circuit.
According to the present invention, it is possible to extend a refresh period by accessing a bank having optimized refresh properties in a partial array self refresh mode. Therefore, the present invention has the advantages of reducing the power consumption of the device and stabilizing data maintenance.